Answered: Why is it preferable to use fragmented…

Why is it preferable to use fragmented memory address translation rather than just translating the addresses in question?

C++ for Engineers and Scientists

4th Edition

ISBN:9781133187844

Author:Bronson, Gary J.

Publisher:Bronson, Gary J.

Chapter10: Pointers

Section10.1: Addresses And Pointers

Problem 12E

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Fundamentals of Input and Output Performance

The I/O subsystem is a component of computer system design that uses buses to assist communication between the Central Processing Unit, Computer Memory/Storage, and Input and Output Devices (that is known as peripheral devices). The I/O subsystem includes disc controllers, tape drives, discs, system buses, and other devices. The I/O database application reads and writes drives using the operating system windows I/O.

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Why is it preferable to use fragmented memory address translation rather than just translating the addresses in question?

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I have this problem from my textbook that I do not understand, despite re-reading the section on segmentation and paging. "The IBM system/370 architecture uses a two-level memory structure and refers to the two levels as segments and pages, although the segmentation approach lacks many of the features described in Chapter 8. For the basic 370 architecture, the page size may be either 2 KB or 4 KB, and the segment size is fixed at either 64 KB or 1 MB. For the 370/XA and 370/ESA architectures, the page size is 4 KB and the segment size is 1 MB. What advantages of segmentation does this scheme lack? What is the benefit of segmentation for the 370?"Can you help me undertand what they are looking for in this explanation?
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Suppose a computer using fully associative cache has 4G bytes of byte-addressable main memory and a cache of 512 blocks, where each cache block contains 128 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? c) To which cache block will the memory address 0x018072 map?
3) Suppose we have a computer that uses a memory address word size of 8 bits. This computer has a 16- byte cache with 4 bytes per block. The computer accesses a number of memory locations throughout the course of running a program. Suppose this computer uses direct-mapped cache. The format of a memory address as seen by the cache is shown below: Tag 4 bits Block 2 bits Offset 2 bits The system accesses memory addresses in this exact order: 0x6E, 0xB9, 0x17, 0xE0, 0x4E, 0x4F, 0x50, 0x91, 0xA8, 0xA9, 0xAB, 0xAD, 0x93, and 0x94. Fill out the following tables: a) Address Hit Reference or Miss Comments b) Show the final contents of cache for direct addressing: Block Cache Contents Tag (represented by address)