Transfer times across memory tiers may be decreased by using buffers. For the given architecture, please list any buffers that may exist between the L1 and L2 caches, and between the L2 cache and the RAM.

Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter6: System Integration And Performance
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Transfer times across memory tiers may be decreased by using buffers. For the given architecture, please list any buffers that may exist between the L1 and L2 caches, and between the L2 cache and the RAM.

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