The next three questions refer to the following system: A certain ISA has a 32-bit word size, uses single word (32-bit) instructions, has 60 opcodes, 32 registers, and 4Gbyte of byte-addressable memory. One group of instructions in this ISA takes the form: OPCODE | DESTINATION REGISTER | SOURCE REG. | Flag | IMMEDIATE VALUE Or OPCODE | DESTINATION REGISTER | SOURCE REG. 1 | Flag | SOURCE REG. 2 A single bit in the instruction ("Flag") is used to differentiate these two addressing modes. Another group of instructions takes the form OPCODE | SOURCE/DESTINATION REGISTERI PC OFFSET Where PC Offset is the 2's complement "distance" from the current PC to the labelled location.
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A: Actually, given expression : M = U/(V*W + X*Y - Z)..
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- A certain ISA has a 32-bit word size, uses single word (32-bit) instructions, has 66 opcodes, 64 registers, and 1G of byte-addressable memory. One group of instructions in this ISA takes the form: OPCODE | DESTINATION REGISTER | SOURCE REG. | Flag | IMMEDIATE VALUE Or OPCODE | DESTINATION REGISTER | SOURCE REG. 1 | Flag | SOURCE REG. 2 A single bit in the instruction ("Flag") is used to differentiate these two addressing modes. Another group of instructions takes the form OPCODE | SOURCE/DESTINATION REGISTER | PC OFFSET Where PC Offset is the 2's complement "distance" from the current PC to the labelled location.Q2- Write a program in assembly language for the 8085 microprocessor to receive one byte of data via the SID and store it at the memory address (3000H to 3009H) using a baud rate of 1200. Information: The 8085 processor operates at a frequency of 3.072 MHz . When receive the required bytes, you must adhere to the following: The bits of two high bits will be received at the beginning of the reception(start bits 1 1 ), after that the data bits will be received, after that the low bit of the stop bit will be received (stop bit 0 ). The following flowchart will help you. The solution must be integrated and include the calculation of the baudrate delay timePCSrc ID/EX EX/MEM Control IF/ID Add Branch MEM/WB Add Shift left 2 RegWrite Instruction Memory Read Address Read Addr 1 Register Read Read Addr Data 1 File Write Addr Data Memory MemtoReg ALUSrc Address Read Data ALU Read Data 2 Write Data Write Data ALU cntrl MemRead Sign Extend 16 32 ALUOP RegDst Figure 3: For EACH of the following registers, indicate how many bits are in the reg- ister, and what control signals are are in the register. he control signals in the diagram are: regWrite, regDest, aluOP, ALUsrc, Branch, MemRead, MemWrite, MemToReg. Register Number of bits Control Signals PC 32 None IF/ID 64* None ID/EX EX/MEM МЕM/WB
- What is the effective address that is targeted by the store instruction whose code word in binary is:101011 01000 10001 1111 1111 1111 1000Assume [$t0]=0x400CQ: Compute the physical address for the specified operand in each of the following instructions. The register contents and variable are as follows: (CS)=D0A00H, (DS)=OBOOH, (SS)=0DO0H, (SI)=OFFOH, (DI)=00BOH, (BP)=00EAH and (IP)=0000H, LIST=D00FOH, AX=4020H, BX=2500H. 1) Destination operand of the instruction MOV LIST (BP+DI], AX 2) Source operand of the instruction MOV CL, [BX+200H] 3) Destination operand of the instruction MOV [DI+6400H] , DX 4) Source operand of the instruction MOV AL, [BP+SI-400H] 5) Destination operand of the instruction MOV (DI+SP] , AX Source operand of the instruction MOV CL, [SP+200H] 7) Destination operand of the instruction MOV [BX+DI+640O0H], CX 8) Source operand of the instruction MOV AL , [BP- 0200H] 9) Destination operand of the instruction MOV [SI] , AX 10) Destination operand of the instruction MOV [BX][DI]+0400H,AL 11) Source operand of the instruction MOV AX, [BP+200H] 12) Source operand of the instruction MOV AL, [SI-0100H] 13) Destination operand…(d) The table below shows the ALUcontrol signal of the datapath we discussed in class. Instruction Funct ALU Орсode ALUop ALU action operation field control Iw 00 load word XXXXXX add 0010 Sw 00 store word XXXXXX add 0010 beq 01 branch equal subtract 0110 XXXXXX R-type 10 add 100000 add 0010 R-type 10 subtract 100010 subtract 0110 R-type 10 AND 100100 AND 0000 R-type 10 OR 100101 OR 0001 R-type 10 set on less than 101010 set on less than 0111 You want to add the bne instruction into the datapath, which already includes the required hardware for the instruction. Write out the ALUop for bne and how you can determine whether the bne results in the branch to be taken.
- Q: Compute the physical address for the specified operand in each of the following instructions. The register contents and variable are as follows: (CS)=0A00H, (DS)=0B00H, (SS)=0D00H, (SI)=OFFOH, (DI)=00BOH, (BP)=00EAH and (IP)=00O0H, LIST=00FOH, AX=4020H, BX=2500H. 1) Destination operand of the instruction MOV LIST [BP+DI] , AX 2) Source operand of the instruction MOV CL, [BX+200H] 3) Destination operand of the instruction MOV [DI+6400H] , DX 4) Source operand of the instruction MOV AL, [BP+SI-400H] 5) Destination operand of the instruction MOV [DI+SP] , AX 6) Source operand of the instruction MOV CL, [SP+200H] 7) Destination operand of the instruction MOV [BX+DI+6400H] , CX 8) Source operand of the instruction MOV AL , [BP- 0200H] 9) Destination operand of the instruction MOV [SI] , AX 10) Destination operand of the instruction MOV [BX][DI]+0400H,AL 11) Source operand of the instruction MOV AX, [BP+200H] 12) Source operand of the instruction MOV AL, [SI-0100H] 13) Destination operand…A certain computer has a memory of 1M words, and each word is 32 bits long. Each instruction is 32 bits long and is consisted of an opcode field, a register address field to specify one of 32 registers, and a memory address field. How large must the register field be? How large must the address field be? How many different opcodes can be supported by this format? Show your reasoningComputer Science A computer uses a memory of 64K words with 16 bits in each word.It has the following registers: PC, AR, TR, AC, DR and IRA memory-reference instruction consists of two words: an 16-bit operation-code(one word) and an address field (in the next word).a-List the sequence of microoperations for fetching a memory reference instructionand then placing the operand in DR. Start from timing signal To.b-Design the logic control gates arrangement to perform the fetch instructions.
- Q: Compute the physical address for the specified operand in each of the following instructions. The register contents and variable are as follows: (CS)=0A00H, (DS)=0BOOH, (SS)=0D00H, (SI)=OFFOH, (DI)=00BOH, (BP)=00EAH and (IP)=0000H, LIST=00F0H, AX=4020H, BX=2500H. 1) Destination operand of the instruction MOV LIST [BP+DI] , AX 2) Source operand of the instruction MOV CL,[BX+200H] 3) Destination operand of the instruction MOV [DI+6400H] , DX 4) Source operand of the instruction MOV AL, [BP+SI-400H] 5) Destination operand of the instruction MOV [DI+SP] , AX 6) Source operand of the instruction MOV CL, [SP+200H] 7) Destination operand of the instruction MOV [BX+DI+6400H] , CX 8) Source operand of the instruction MOV AL , [BP- 0200H] 9) Destination operand of the instruction MOV [SI] , AX 10) Destination operand of the instruction MOV [BX][DI]+0400H,AL 11) Source operand of the instruction MOV AX, [BP+200H] 12) Source operand of the instruction MOV AL, [SI-O100H] 13) Destination operand…D-Latch is a simple clocked memory element in which the output is equal to the stored state inside the element. In D-Latch the state is changed whenever the appropriate inputs change and the clock is asserted. A D-Latch has two inputs and two outputs. The inputs are the data value to be stored and a clock signal that indicates when the latch should read the value on the data input and store it. The outputs are simply the value of the internal state and its complement. When the clock input is asserted, the latch is said to be open, and the value of the output becomes the value of the data input. When the clock input is de-asserted, the latch is said to be closed, and the value of the output is whatever value was stored the last time the latch was open. What is the difference between DFF and D-Latch? Can one chip be used for constructing the other? Explain.The memory unit of a computer has 2M words of 32 bits each. The computer has an instruction format with 4 fields: an opcode field; a mode field to specify 1 of 4 addressing modes; a register address field to specify one of 9 registers; and a memory address field. Assume an instruction is 32 bits long. Answer the following: a) How large must the mode field be?