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- The most common technique to caneg analog to digital data is called Pulse Code Modulation(PCM). What are the 3 processes of a PCM? (in order)Assuming that a certain ASM chart has 5 states, the size of each multiplexer required to implement this circuit using the multiplexer design approach should be: Select one: O a. Four to one. O b. Eight to one. O . None of the given. O d. Two to one.3. What happens if the inverting & non-inverting i/p of the comparator interchanged? 4. Are there any limitations of such a vCO? Explain 5. Explain how a sine wave can be generated from such a VCO circuit. 6. List some applications for such a Vco.
- c) What does the ASYNC input to the 8284A accomplish?Construct MOD 12 asynchronous counter. What will be the output frequency, if the input frequency is 1 MHz. If the counter is at state 6, what will be the count after 60 pulses.A pulse width modulated output is configured with an 40MHz clock, a prescaler of 80 and a count register of 1000. What is the frequency of the PWM signal?
- A certain counting type 12 bit ADC operates with FSR = 0 to 10 V and clock frequency folk = 1 MHz. Determine the dynamic range of the converter, conversion time, conversion rate and Nyquist frequency of the converter.4. The LM317 is an example of an IC A. three-terminal negative voltage regulator B. variable positive voltage regulator C. fixed positive voltage regulator D. switching regulator 5. Analog multiplexer called time-division multiplexer because of: A. It required fixed time period to operate. B. The signals are time overlapped throughout the output. C. The MOSFETS turning on and off half of the time. D. The input signals are time variants. 6. The basic difference between a series regulator and a shunt regulator is: A. the amount of current that can be handled B. the position of the control element C. the type of sample circuit D. the type of error detectorIn ADC circuit ,the input will be ........... signal.
- Offset voltage compensating network is connected in between pin number .......... &.. of LM741 op-amp .... O 1 and 4 O 1 and 5 O 2 and 3 O 4 and 7(d) In a certain clock generation circuitry, the input range of the PLL is 3MHZ – 6MHZ. If the input clock is 16MHZ. what are the best values for the divider and PLL setting to get 20MHZ at the output of the clock generation circuitry?Define moore state machine. Draw Mealy state diagram of sequnce 1111 with overlapping condition.