QUESTION 3 The effective access time for a machine with a page fault probability of 3%, memory access time (tą) of 200 nanoseconds, and a page fault (tf) time of 50 milliseconds is a. 1500194 b. 1000196 O C. None of the listed d. 250000
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- Calculate the effective access time for a demand-paged memory given a memory access time of 100 nanoseconds, a page fault service time of 6,000,000 nanoseconds, and a page-fault rate of 1 page fault out of every 10,000 access attempts.I am trying to better understand memory access in computers, please answer the sample question below. Assume that the page table can held in registers of the MMU. It takes 8 ms (milliseconds)to service a page fault if there is an empty frame or if the replaced page is not altered, and20 ms if the replaced page is altered. Memory access time is 100 ns (nanoseconds). It has been empirically measured that the page to be replaced is altered 75% of the time.Obtain the maximum probability of page fault for an effective memory access time ≤ 200ns.What happens if VA page 30 is written even if an instruction was not accepted? An instance of a software-managed TLB would outperform a hardware-managed TLB in the following cases:
- (b) Consider a paging system with the page table stored in memory. If a memory referencetakes 200 nano seconds, how long does a paged memory reference take? If we add a TLB,and 75% of all page references are found in the TLB, what is the effective memory referencetime? (Assume that it takes zero time to find an entry in the TLB if it is already present).3. If we have an 8 bit microcontroller that has 4kB of instruction memory starting at address 0x0000, and 2kB of data memory immediately above that, what is the next available byte in our address map?Question 1 Suppose that the WSClock page replacement algorithm uses a tau (t) of ten ticks, and the system state is the following: Page Number Time stamp (time of last use) V R M 10 60 1 0 1 11 90 1 1 0 12 90 1 1 1 13 70 1 0 0 14 40 0 0 0 where the three flag bits V, R, and M stand for Valid, Referenced, and Modified, respectively. (a) If a clock interrupt occurs at tick 100 (current virtual time), show the contents of the new table entries. Briefly explain any changes. (You can omit entries that are unchanged.) (b) Suppose that instead of a clock interrupt, a page fault occurs at tick 100 due to a read request to page 14. Show the contents of the new table entries. Explain which page will be evicted, giving the changes made to that page in the table, and explain the changes made to page 14. (You can omit entries that are unchanged.)
- A microprocessor scans the status of an output I/O device every 20 ms. This is accom- plished by means of a timer alerting the processor every 20 ms. The interface of the device includes two ports: one for status and one for data output. How long does it take to scan and service the device given a clocking rate of 8 MHz? Assume for sim- plicity that all pertinent instruction cycles take 12 clock cycles.You are given the following data about a virtual memory system:(a)The TLB can hold 1024 entries and can be accessed in 1 clock cycle (1 nsec).(b) A page table entry can be found in 100 clock cycles or 100 nsec.(c) The average page replacement time is 6 msec.If page references are handled by the TLB 99% of the time, and only 0.01% lead to a page fault, what is the effective address-translation time?Question 2: Write the MIPS code for the given Hexadecimal Machine Code that starts at memory address 0x40000. Line1: 0x0080082A Line2: 0x14200002 Line3: 0x2084FFFF Line4: 0x08010005 Line5: 0x20840001 Line6: 0x1480FFFA Line7: 0x03E00008 Line8: 0x0C010000
- Calculate the effective access time for a demand-paged memory given a memory access time of 100 nanoseconds, a page fault service time of 6,000,000 nanoseconds, and a page-fault rate of 1 page fault out of every 10,000 access attempts. You must show your calculations to receive full credit on this question.You are given the following data about a virtual memory system:(a) The TLB can hold 512 entries and can be accessed in 1 clock cycle (1nsec).(b) A page table entry can be found in 100 clock cycles or 100 nsec.(c) The average page replacement time is 9 msec.If page references are handled by the TLB 99% of the time, and only 0.01%lead to a page fault, what is the effective address-translation time?In a dynamic random access memory (DRAM) computer chip, each memory cell chiefly consists of a capacitor for charge storage. Each of these cells represents a single binary-bit value of 1 when its 35-fFfcapacitor (1fF=10^−15F) is charged at 1.5 V, or 0 when uncharged at 0 V. A)When it is fully charged, how many excess electrons are on a cell capacitor's negative plate? B) After charge has been placed on a cell capacitor's plate, it slowly "leaks" off (through a variety of mechanisms) at a constant rate of 0.30 fC/s. How long does it take for the potential difference across this capacitor to decrease by 1.0% from its fully charged value? (Because of this leakage effect, the charge on a DRAM capacitor is "refreshed" many times per second.) Express your answer to two significant figures and include the appropriate units.