Q1: A/ Design and draw a logic circuit that compares between two 3-bit binary numbers. The circuit produces 0 if the two numbers are equal and 1 otherwise. Then, redraw the circuit using NAND gates only.
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- 5- Determine an alternative method for implement the full-adder. Hint: Write the expressions of the circuit and simplify using icarnaugh map.Then implement using AND-OR gates. 6- Design a logic cct using NAND gate and convert BCD code to Excess-3code.(a) Figure Q.4 (a) shows a combinational logic cireuit with output, Z and Table Q.4(a) depicts the delay for each logic gate in nanoseconds (ns). Determine the critical path and critical path delay in nanoseconds (ns). В Figure Q.4(a) Table Q.4 (a) Logic Gate NOT Delay (ns) 4 OR 8 AND 16 NAND 12 NOR 10 XOR 28 XNOR 32Q1) For the circuits shown in figures 1 and 2: 1. What is the function of output? 2. Find the max. and min. Vol. value? 3. Determine the static power (avg.)? 4. Design equivalent logic circuit by CMOC logic circuits? Use VDD= 10 V. Vr.o=1V. Vru-1V. (W/L)o= (5/2), (W/L)L (20/2), RD = 40k, KL = 10P A/V^2 and KO = 40pA/V`2? Figure 1 5 VDD RD Figure 2 बदना दे
- A certain digital circuits designed to operate with voltage levels of -0.2Vdc and -3.0Vdc. If H= 1 =-0.2 Vdc and L =0 =-3.0 Vdc, is this positive logic or negative logic ? H=+5.0Vdc. and. L=+1.0Vdc What are the voltage levels between fall and rise times are measured? What is the value of Duty cycle H if the waveform is high for 2 ms and low for 5 ms?Draw the the basic logic diagram of decimal to BCD Encoder .(a) Consider a combinational logic circuit in Figure Q.2 (a).i and Q.2 (a).ii. Determine the Boolean equation for the output Y and then, replace the circuit with a single logic gate. Figure Q.2 (a)i Vpp Voo Figure Q.2 (a)ii
- F(a,b,c,d)=ab'+c'd'+a'cd' Perform the function in accordance with the following styles using the Karnaugh diagram. Draw each simplification using the corresponding logic gates. a) only or not (NOR) b) and not just (NAND) c) OR-NAND d) AND-NOR1.1 Given the timing diagram for 3-bit input A and two outputs, S and C in Figure la, where A2 is the MSB and Ao is the LSB. Assume the output for the other input conditions is don't cares (i.c. X). Determine the minimum logic circuit using NAND logic configuration. Az Ac S C Figure la1 Design and draw the logic diagram for a two-input NAND gate using one two-input AND and one NOT gate. Include the pin numbers on the gate inputs and outputs.