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- A circuit which connects one of 2^n data lines to one output line is defined as a * Decoder MUX DEMUX ROM O EncoderBinary Counters Objective: Design, construct, and test a three-bit counter that counts up or down. A disable input D determines whether the counter is on or off. • If D=1, the counter is disabled and remains at its present count even thoughclock pulses are applied to the flip-flops. • If D-0, the counter is enabled and a second input, x, determines the directionof the count. • If x=1, the circuit counts the sequence 00, 01, 10,11 and the count repeats. • If x=0, the circuit counts the sequence 11, 10, 01, 00 and the count repeats. (Do not use D to disable the Clock) Note: Design the sequential circuit with D and x as inputs. Submission: Reports must include all schematics and cost of design. Compare your results with other solutions. (Costs, design....). Define why your design is better.Assume a 4-by-2 encoder with 4 active-HIGH inputs (D3, D2, D1 and DO) and 2 active-HIGH outputs (X1 and XO) has basic operation as follows: Input: D3= 1 ==> Output: X1 =1, X0=1 Input: D2= 1 ==> Output: X1 =1, X0=0 Input: D1= 1 ==> Output: X1 =0, X0=1 Input: D0= 1 ==> Output: X1 = 0, X0=0 The priority encoder has priority ranking as the following: DO (highest), D1, D2, D3 (lowest). Complete Table below that shows the summarized operation of the priority encoder 4-by-2 Priority Encoder Input D3 D2 DI 1 + 1 + + + + + 1 ◆ DO x1 ΧΟ + 11 10 01 100
- Computer Science Create schematics for each Coding technique (you can use different components, Logic Gates, Encoder, etc.) a. Screenshot your schematics (Unipolar, Polar, Bipolar, Multilevel, and Multitransition line encoding each respectively) b. Simulate with different Input (series of ones and zeros) and provide the output screenshot.2. In computer systems, it is often necessary to transfer n bit data items. Design a circuit to per- form a 4 bit shift register that can be used to either transfer all the bits at once or transfer one bit at a time. Please use D flipflops for your implementation. Please explain the operation of the same. Write a simple HDL program that can implement the same.Q2: Design an asynchronous state machine, which has two inputs and two output (Z1Z2). If the sequence (10, 11) occurs, the output will be Z (10) and then reset to zero. If the sequence (01, 11) occurs, the output will equal to (01) and then Z1 Z2 will equal to (00).
- Design a four-input priority encoder with inputs as in Table 4.8 , but with input D 0 having the highest priority and input D 3 the lowest priority.Q1: Define the following: Multiplexer, Demultiplexer, Decoder, Encoder.In digital electronics and modern computer hardware, a flip-flop is a sequential digital circuit used as a basic memory element. It has two stable states and can be used to store state information. One of its states represents ‘1’ while the other represents ‘0’. The most common types of flip-flops are SR-flip-flop, JK-flip-flop, and D flip-flop. When used in a finite-state machine, the output and next state depend not only on its current input but also on its current state (and hence, previous inputs). Stage 2 Stage 1 Figure 1 D-Flip-flop with clock pulse (CP) Figure 1 shows a D flip-flop with clock pulse (CP). D is directly passed from stage1 to stage 2 through the NAND gate and passed as inverted through gate 5 and gate 4. The input D is always sampled when the system CP is 1. Considering the memory element in Figure 1, perform the following tasks: Design FSM for the Figure 1
- In digital electronics and modern computer hardware, a flip-flop is a sequential digital circuit used as a basic memory element. It has two stable states and can be used to store state information. One of its states represents ‘1’ while the other represents ‘0’. The most common types of flip-flops are SR-flip-flop, JK-flip-flop, and D flip-flop. When used in a finite-state machine, the output and next state depend not only on its current input but also on its current state (and hence, previous inputs). Stage 2 Stage 1 Figure 1 D-Flip-flop with clock pulse (CP) Figure 1 shows a D flip-flop with clock pulse (CP). D is directly passed from stage1 to stage 2 through the NAND gate and passed as inverted through gate 5 and gate 4. The input D is always sampled when the system CP is 1. Considering the memory element in Figure 1, perform the following tasks: design FSM for 8-bit shift register and simulate it using C++, which can multiply or divide the…Design a 4-bit Asynchronous Counter up/down (Note: Please have the design be a clear outline or printed in order to attach it to the file)Data distributors are basically the same as(a) decoders (b) demultiplexers(c) multiplexers (d) encoders