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(i) Below (figure 1) is an example of a VHDL code for a multiplexer. "00000010000001"WHEN "10000",-Input A "00000010000001"WHEN "10001",- "00000010000001"WHEN "10010". "00000010000001"WHEN "10011". "00000011001111"WHEN "10100", "00000011001111"WHEN "10101", "00000011001111"WHEN "10110", "00000011001111"WHEN "10111", "10011110000001"WHEN "11000", "10011110000001"WHEN "11001", --multiplexer.vhd -Common Multiplexer LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY multiplexer IS PORT(e1, d3, d2, dl, d0 : IN STD LOGIC: a,b.c,d,e.f.g.h.ij.k.m,n:OUT STD_LOGIC);: END multiplexer; ARCHITECTURE mult OF multiplexer IS SIGNAL input : STD LOGIC_VECTOR (4 downto 0); SIGNAL output : STD LOGIC VECTOR (13 downto 0); BEGIN input c el & d3 & d2 & d1 & do; WITH input SELECT output ce "00000010000001"WHEN "00000",--Input B "00000011001111"WHEN "00001", "10011110000001"WHEN "00010", "10011111001111"WHEN "00011", "00000010000001"WHEN "00100", "00000011001111"WHEN "00101", "10011110000001"WHEN "00110", "10011111001111"WHEN "00111". "00000010000001"WHEN "01000", "00000011001111"WHEN "01001". "10011110000001"WHEN "01010", "10011111001111"WHEN "01011", "00000010000001"WHEN "01100", "00000011001111"WHEN "01101", "10011110000001 WHEN "01110", "10011111001111"WHEN "01111",- "10011110000001"WHEN "11010", "10011110000001"WHEN "11011", "10011111001111"WHEN "11100", "10011111001111"WHEN "11101", "10011111001111"WHEN "11110", 10011111001111"WHEN "11111"; -"00000010000001" -00 -"00000011001111"-01 -"10011110000001" -10 --"10011111001111"-11 --Separate the output vector to make individual pin outputs. he output(13); ie output(12): je output(11): kc= output(10); |e output(9): mc= output(8); nc output(7); a<= output(6); be output(5); C= output(4); de output(3): ec output(2): fe output(1): g= output(0); END mult; Figure 1 (a) How many bits of input(s) and output(s) are declared in this code? Which line of code supports your answer?

(i) Below (figure 1) is an example of a VHDL code for a multiplexer. "00000010000001"WHEN "10000",-Input A "00000010000001"WHEN "10001",- "00000010000001"WHEN "10010". "00000010000001"WHEN "10011". "00000011001111"WHEN "10100", "00000011001111"WHEN "10101", "00000011001111"WHEN "10110", "00000011001111"WHEN "10111", "10011110000001"WHEN "11000", "10011110000001"WHEN "11001", --multiplexer.vhd -Common Multiplexer LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY multiplexer IS PORT(e1, d3, d2, dl, d0 : IN STD LOGIC: a,b.c,d,e.f.g.h.ij.k.m,n:OUT STD_LOGIC);: END multiplexer; ARCHITECTURE mult OF multiplexer IS SIGNAL input : STD LOGIC_VECTOR (4 downto 0); SIGNAL output : STD LOGIC VECTOR (13 downto 0); BEGIN input c el & d3 & d2 & d1 & do; WITH input SELECT output ce "00000010000001"WHEN "00000",--Input B "00000011001111"WHEN "00001", "10011110000001"WHEN "00010", "10011111001111"WHEN "00011", "00000010000001"WHEN "00100", "00000011001111"WHEN "00101", "10011110000001"WHEN "00110", "10011111001111"WHEN "00111". "00000010000001"WHEN "01000", "00000011001111"WHEN "01001". "10011110000001"WHEN "01010", "10011111001111"WHEN "01011", "00000010000001"WHEN "01100", "00000011001111"WHEN "01101", "10011110000001 WHEN "01110", "10011111001111"WHEN "01111",- "10011110000001"WHEN "11010", "10011110000001"WHEN "11011", "10011111001111"WHEN "11100", "10011111001111"WHEN "11101", "10011111001111"WHEN "11110", 10011111001111"WHEN "11111"; -"00000010000001" -00 -"00000011001111"-01 -"10011110000001" -10 --"10011111001111"-11 --Separate the output vector to make individual pin outputs. he output(13); ie output(12): je output(11): kc= output(10); |e output(9): mc= output(8); nc output(7); a<= output(6); be output(5); C= output(4); de output(3): ec output(2): fe output(1): g= output(0); END mult; Figure 1 (a) How many bits of input(s) and output(s) are declared in this code? Which line of code supports your answer?

Electricity for Refrigeration, Heating, and Air Conditioning (MindTap Course List)
Electricity for Refrigeration, Heating, and Air Conditioning (MindTap Course List)
10th Edition
ISBN:9781337399128
Author:Russell E. Smith
Publisher:Russell E. Smith
Chapter17: Commercial And Industrial Air-conditioning Control Systems
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(i) Below (figure 1) is an example of a VHDL code for a multiplexer. --multiplexer.vhd --Common Multiplexer LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY multiplexer IS PORT(el, d3, d2, d1, d0 : IN STD_LOGIC; a,b.c,d,e,f.g.h.ij.k,lm,n:OUT STD LOGIC); END multiplexer; ARCHITECTURE mult OF multiplexer IS SIGNAL input : STD LOGIC_VECTOR (4 downto 0); SIGNAL output : STD LOGIC_VECTOR (13 downto 0); BEGIN input ca el & d3 & d2 & d1 & d0; WITH input SELECT "00000010000001"WHEN "10000",--Input A "00000010000001"WHEN "10001",- "00000010000001"WHEN "10010",- "00000010000001"WHEN "10011",- "00000011001111"WHEN "10100" "00000011001111"WHEN "10101 "00000011001111"WHEN "10110" "00000011001111"WHEN "10111" "10011110000001"WHEN "11000" "10011110000001"WHEN "11001" "10011110000001"WHEN "11010, "10011110000001"WHEN "11011" "10011111001111"WHEN "11100" "100111110011i1"WHEN "11101",- "10011111001111"WHEN "11110",-- "10011111001111"WHEN "11111":-. "00000010000001" -00 --"00000011001111"-01 "10011110000001" -10 "10011111001111" -11 --Separate the output vector to make individual pin outputs. h<= output(13); ice output(12); j<« output(11): kc- output(10); |<e output(9); mc= output(8); nc output(7); a c= output(6): b<= output(5); C= output(4); dc output(3); ec= output(2); fe output(1); g<= output(0); END mult: output c "00000010000001"WHEN "00000",--Input B "00000011001111"WHEN "00001",-- "10011110000001"WHEN "00010",- "10011111001111"WHEN "00011", "00000010000001"WHEN "00100", "00000011001111"WHEN "00101", "10011110000001"WHEN "00110", "10011111001111"WHEN "00111", "00000010000001"WHEN "01000", "00000011001111"WHEN "01001 "10011110000001"WHEN "01010", "10011111001111"WHEN "01011". "00000010000001"WHEN "01100", "00000011001111"WHEN "01101",- "10011110000001" WHEN "01110",- "100111110011l1"WHEN "01111",-- Figure 1 (a) How many bits of input(s) and output(s) are declared in this code? Which line of code supports your answer?
Transcribed Image Text:(i) Below (figure 1) is an example of a VHDL code for a multiplexer. --multiplexer.vhd --Common Multiplexer LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY multiplexer IS PORT(el, d3, d2, d1, d0 : IN STD_LOGIC; a,b.c,d,e,f.g.h.ij.k,lm,n:OUT STD LOGIC); END multiplexer; ARCHITECTURE mult OF multiplexer IS SIGNAL input : STD LOGIC_VECTOR (4 downto 0); SIGNAL output : STD LOGIC_VECTOR (13 downto 0); BEGIN input ca el & d3 & d2 & d1 & d0; WITH input SELECT "00000010000001"WHEN "10000",--Input A "00000010000001"WHEN "10001",- "00000010000001"WHEN "10010",- "00000010000001"WHEN "10011",- "00000011001111"WHEN "10100" "00000011001111"WHEN "10101 "00000011001111"WHEN "10110" "00000011001111"WHEN "10111" "10011110000001"WHEN "11000" "10011110000001"WHEN "11001" "10011110000001"WHEN "11010, "10011110000001"WHEN "11011" "10011111001111"WHEN "11100" "100111110011i1"WHEN "11101",- "10011111001111"WHEN "11110",-- "10011111001111"WHEN "11111":-. "00000010000001" -00 --"00000011001111"-01 "10011110000001" -10 "10011111001111" -11 --Separate the output vector to make individual pin outputs. h<= output(13); ice output(12); j<« output(11): kc- output(10); |<e output(9); mc= output(8); nc output(7); a c= output(6): b<= output(5); C= output(4); dc output(3); ec= output(2); fe output(1); g<= output(0); END mult: output c "00000010000001"WHEN "00000",--Input B "00000011001111"WHEN "00001",-- "10011110000001"WHEN "00010",- "10011111001111"WHEN "00011", "00000010000001"WHEN "00100", "00000011001111"WHEN "00101", "10011110000001"WHEN "00110", "10011111001111"WHEN "00111", "00000010000001"WHEN "01000", "00000011001111"WHEN "01001 "10011110000001"WHEN "01010", "10011111001111"WHEN "01011". "00000010000001"WHEN "01100", "00000011001111"WHEN "01101",- "10011110000001" WHEN "01110",- "100111110011l1"WHEN "01111",-- Figure 1 (a) How many bits of input(s) and output(s) are declared in this code? Which line of code supports your answer?
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