For the up system, suppose that the total number of clock N and the total number of memory cycle M is taken by each instruction. 1. Suppose we have to insert W wait state per memory cycle. What will be the actual total number of clock cycle per instruction?
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- A microprocessor scans the status of an output I/O device every 20 ms. This is accom- plished by means of a timer alerting the processor every 20 ms. The interface of the device includes two ports: one for status and one for data output. How long does it take to scan and service the device given a clocking rate of 8 MHz? Assume for sim- plicity that all pertinent instruction cycles take 12 clock cycles.Assume for a given program, 60% of the executed instructionsare of Class A, 10% are of Class B, and 30% are of Class C. Furthermore,assume that an instruction in Class A requires 3 cycles, an instruction inClass B requires 2 cycles, and an instruction in Class C requires 2 tocomplete. i. Compute the overall CPI for this program.ii. Compute the clock rate of the CPU when the time it takes tocomplete 20 instructions is 1.73 ???????????A CPU takes 'x' number of clock cycles per one instruction; the Corresponding Pipelined CPU takes 2,3,4 and 1, clocks in IF, ID, PO and WB stages. To get the Speed-up 2.5, the 'x' value is
- Suppose we have two implementations:Machine A has a clock cycle time of 10 ns. and a CPI of 2.0. Machine B has aclock cycle time of 20 ns. and a CPI of 1.2. Which machine is faster for thisprogram, and how much in percentage? Consider that the total instruction in the program is 1x10^9 or about 1,000,000,000 set of instructions since the cycle time is running in nanoseconds.Two interrupts have execution times of 7.5us and 10 us. Both occur at the same rate, Find the maximum frequency that they can occur to maintain a combined CPU% less than 1.5%?Q. What is the baseline performance (in cycles, per loop iteration) of the code sequence in if no new instruction’s execution could be initiated until the previous instruction’s execution had completed? Ignore front-end fetch and decode. Assume for now that execution does not stall for lack of the next instruction, but only one instruction/cycle can be issued. Assume the branch is taken, and that there is a one-cycle branch delay slot. Latencies beyond single cycle: Latencies beyond single cycle:Memory LD +6Memory SD +4Integer ADD, SUB +1Branches +2fadd.d +4fmul.d +6fdiv.d +10Execution codeLoop : fld f2, 0(Rx)I0: fdiv.d f8, f2, f0I1: fmul.d f2, f6, f2I2: fld f4, 0(Ry)I3: fadd.d f4, f0, f4I4: fadd.d f10, f8, f4I5: fsd f10, 0(Ry)I6: addi Rx, Ry, 8I7: addi Ry, Ry, 8I8: sub x20, x4, RxI9: bnz x20, Loop Q. Think about what latency numbers really mean—they indicate the number of cycles a given function requires to produce its output. If the overall pipeline stalls for the latency cycles of…
- Question Q: For a basic computer that is currently running in its timing TO of execution for an instruction that is located in memory location 366. The content of AC is (212) and the content of memory locations are as follow: [memory location: content]: [365:9473], [366:7010], [367:5431], [368:4620], [431:1A23], [620:C80D]. Answer the following questions that examine the contents of PC, AR, AC, DR and IR after the end of execution for the next instruction. (Note: all numbers are in Hexadecimal.) p 4:33 The content of AC after the end of * :execution for the next instruction is 700 O 620 320 O None of the choices O 4:35 /Question Q: For a basic computer that is currently running in its timing TO of execution for an instruction that is located in memory location 366. The content of AC is (212) and the content of memory locations are as follow: [memory location: content]: [365:9473], [366:7010], [367:5431], [368:4620], [431:1A23], [620:C80D]. Answer the following questions that examine the contents of PC, AR, AC, DR and IR after the end of execution for the next instruction. (.(Note: all numbers are in Hexadecimal The content of IR after the end of execution :for the next instruction is 4620 O 9473 5431 None of the choices 7010 OOn the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?
- The table below shows instruction-type breakdown for different programs. Using this data, you will be exploring the performance trade-offs for different changes made to an MIPS processor. Compute Load Store Branch Total Program1 600 600 200 50 ? • Program2 900 500 100 200Find the base and limit register value for each job in the memory when the order of the job going into the memory is Job 2, Job 4, Job 1, Job 3.Also tell what will happen if CPU request for the base address 306460 and limit address480215. please consider this image for solving the problemConsider the two computers A and B with the clock cycle times 100 ps and 150 ps respectively for some program. The number of cycles per instruction (CPI) for A and B are 2.0 and 1.0 respectively for the same program. Which computer is faster and how much? Va A is 1.33 times faster than B b) B is 1.22 times faster than A c) A is 1.23 times faster thanB d) B is 1.33 times faster than A