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- First, you must create a logic circuit using only basic gates such as AND, OR, NOR, NAND, NOT, etc. to implement an ADDER capable of adding two 4 bit binary numbers. Second, you must create a logic circuit using only basic gates such as AND, OR, NOR, NAND, NOT, etc. to implement a Subtractor that is capable of subtracting the second number from the first, by converting the second number into its 2's complement form and then adding the resulting number to the first number. You do not need to worry about accomodating the addition or subtraction of negative numbers. Finally, create a limited ALU (Arithmetic logic unit) circuit using Logism that implements a Full Adder circuit capable of adding 2 – 4 bit binary numbers and subtracting 2- 4 bit binary numbers. Also, implement the ability to select a bitwise AND operation and a bitwise OR operation. For the ALU it is acceptable to use the Adder and Subtractor circuits that are listed under the "Arithmetic" folder in Logism. (Logism tips and…Design a 2-bit comparator. The comparator input has two 2-bit numbers A and B. A consists of 2 bits a1 and a0. B consists of 2 bits b1 and b0. The comparator has three outputs Z2, Z1, Z0. a. Show the truth table for this comparator. b. Write the logic equation for Z2 that are true if only if A < B c. Write the logic equation for Z1 that are true if only if A > B d. Write the logic equation for Z0 that are true if only if A = B e. Show the logic design for this comparator using the minimum number of AND, OR, and Inverters. f. Verify your design using Logisim.1 The following diagram represents a multiplier circuit that takes 2-bit binary numbers A1 A0 and BB1 B0 and produces an output binary number Y3 Y2 Y1 YO (LSB) that is equal to the arithmetic product of the two input numbers. Design this logic circuit using a decoder (You can use any type of a decoder). A1 Y3 Ao Multiplier Circuit Y2 (LSB) В Bo (LSB) |(LSB) Y,
- Answer this question, part (1), (2) & (3). Design a combinational logic circuit that converts a three-bit binary number from code A to code B, according to the table on the right. Answer the following questions: Code A Code B 000 000 001 001 011 010 010 011 110 100 111 101 101 110 100 111 Construct the truth table for the circuit. Derive the Sum-of-Products (SoPs) Boolean expression for each of the circuit outputs. Using Boolean algebra, simplify the expression you obtained in Part 2 above.Design a combinational circuit that detects an error in the representations of a decimal digit in Binary Coded Decimal (BCD). In other words, obtain a logic diagram for a circuit that accepts the four BCD bits as input and whose output is when the inputs contain any one of the six unused bit combinations in the BCD code.5. Design a logic circuit with 3-bit inputs A, B, C that produces an output W, X, Y, Z that is equal to the input + 6 (110) in binary. For example If the input is equal to 5 decimal then the output should be 5+6=11 decimal, the circuit will take all numbers in binary form and the output will also be in binary (101)B + (110)B=(1011)B
- Design a circuit that uses 4-bit full adders and AND gates. Given two 8-bit signed 2s-complement numbers A and B and a binary input signal M, your circuit should produce an 8-bit signed 2s-complement result R, as follows: if (M == 0) R = A; else R = A + B + 1;AO- For the above given logic circuit, the output Y value is =1 when the inputs of A, B, and C are a. None of these O b. A=1, B=1, C=1 O c. A=1, B=1, C=0 O d. A=1, B=0, C=1Q1. Construct the truth table of a full adder which calculate [S, Cout] = A + B + Cin where A = A1Ao is a 2- bit number, B is a 1-bit number, Cin is a 1-bit carry-in S = SiSo is a 2-bit sum and Cout is a 1-bit carry-out, and implement its circuit using no more than 20 logic gates.
- Question 2: A combinational circuit has 4 inputs (A, B, C, D) and 1 output (F). ABCD represent a majority function. The output of the majority function is equal to 1 if the input variables have more 1's than O's, otherwise the output is 0. a. Construct the truth table of the required circuit. b. Implement the minimized expression of F using 3-level all NAND gate circuit. Implement a 2-1Multiplexer using three-state buffers.stion : 1/1 a Implement the function F (A, B, C) = E(1, 2, 4, 5, 7) a. Using a 2x4 decoder and any logic gates. b. Using a 4:1 multiplexer. P Type here to search 60A combinational logic circuit has an output F=a'b'c+a'c'd'+bc'd+acd. A * ;static one hazard occurs when abcd=0100 changed to 0101 abcd=1101 changed to 1111 abcd=0101 changed to 0100 abcd=0000 changed to 0010