02Design a 2-digit decade counter that counts from 00 to 59 and repeats. Use two cascaded synchronous binarycounters (74LS163) and other basic logic gates to implement. Simulate the complete counter circuit by OrCADand PSPICE. Capture the circuit schematic and the simulated waveform.. (Define the simulation timings for atleast one full counting cycle from 0 to 59 and back to 0.)Q3Repeat Q2, modify the design to implement a 2-digit decade counter that counts from 33 to 77 and repeats. Usetwo cascaded synchronous binary counters (74LS163) and other basic logic gates to implement. Simulate thecomplete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform.(Define the simulation timings for at least one full counting cycle from 33 to 77 and back to 33.) a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade countershould be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulatethe complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulatedwaveform. (Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.)(Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME andOFFTIME accordingly for the clock source.)1/6PatDigClockPart ListOFFTIME = SuS DSTM1ONTIME =DELAY=STARTVAL = 0OPPVAL = 1SusEUKFleStimACLbrajesDesign Cacheb) Read the specification of 74LS47 (BCD-to-7-Segment Decoder shown in Appendix) to see how the logic ICoperates to drive a 7-segment LED display. Draw the circuit connection of the decade counter in (a) and thedecoder to display the count value on the 7-segment LED display. Further explain why common anodeconfiguration is needed for our 7-segment display rather than the common cathode configuration.

According to guidelines we need to solve only the first question. According to the question we have…

Design a 2-digit decade counter that counts from 00 to 59 and repeats. Use two cascaded synchronous binary counters (74LS163) and other basic logic gates to implement. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. . (Define the simulation timings for at least one full counting cycle from 0 to 59 and back to 0.)

Design a 2-digit decade counter that counts from 00 to 59 and repeats. Use two cascaded synchronous binary counters (74LS163) and other basic logic gates to implement. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. . (Define the simulation timings for at least one full counting cycle from 0 to 59 and back to 0.)

Electric Motor Control

10th Edition

ISBN:9781133702818

Author:Herman

Publisher:Herman

Chapter22: Sequence Control

Section: Chapter Questions

Problem 6SQ: Draw a symbol for a solid-state logic element AND.

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