Complete the below timing diagram for the following sequence of bus transactions: o device A wants to do a read transaction and has asserted REQ A# at the start of cycle 0 o device B wants to do a write transaction and has asserted REQ B# at the start of cycle 0 o device C wants to do a read transaction and has asserted REQ C# at the start of cycle 0 Make the following assumptions: o devices A, B only want to transfer one piece of datum, C wants to transfer 2 pieces of datum. o the arbiter uses a round-robin priority scheme where currently Device B has the highest priority and device A has the lowest priority. o for A transaction, both the initiator and target are ready as soon as possible. o for B transaction, the target is not ready for 2 clock cycles. o for C transaction: during the first transfer both initiator and target are ready as soon as possible. during the second transfer the initiator is not ready for 1 clock cycle.

Computer Networking: A Top-Down Approach (7th Edition)
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ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
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Complete the below timing diagram for the following sequence of bus transactions:
o device A wants to do a read transaction and has asserted REQ A# at the start of cycle 0 o device B wants to do a write transaction and has asserted REQ B# at the start of cycle 0 o device C wants to do a read transaction and has asserted REQ C# at the start of cycle 0 Make the following assumptions:

o devices A, B only want to transfer one piece of datum, C wants to transfer 2 pieces of datum.

o the arbiter uses a round-robin priority scheme where currently Device B has the highest priority and device A has the lowest priority.

o for A transaction, both the initiator and target are ready as soon as possible. o for B transaction, the target is not ready for 2 clock cycles.
o for C transaction:

  1. during the first transfer both initiator and target are ready as soon as possible.
  2. during the second transfer the initiator is not ready for 1 clock cycle.

Before cycle 0 starts, the previous bus master de-asserts IRDY# so it is free

CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
Req A#
Req B#
Gnt A#
Gnt B#
----+-
+
4
Transcribed Image Text:CLK FRAME# AD C/BE# IRDY# TRDY# DEVSEL# Req A# Req B# Gnt A# Gnt B# ----+- + 4
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