(b)Consider a system with multiple level memory as in Table Q52Table Q52'-.(i)(ii)Value90 %5 ns96%ComponentCache Hit RateCache Hit TimeOff Chip Cache Hit RateOff Chip Cache Hit TimeMain Memory Hit RateMain Memory Hit TimeMain Memory Miss PenaltyCalculate the Average Memory Access Time for this system.10 ns99.8%60 ns10 000 nsCalculate the Global Miss Rate for this system.

Please refer below for your reference: The average Memory access time for this system is given as :…

(b) Consider a system with multiple level memory as in Table Q52 Table Q52 (i) (ii) Component Cache Hit Rate Cache Hit Time Off Chip Cache Hit Rate Off Chip Cache Hit Time Value 90% 5 ns 96% 10 ns Main Memory Hit Rate 99.8% 60 ns Main Memory Hit Time Main Memory Miss Penalty 10 000 ns Calculate the Average Memory Access Time for this system. Calculate the Global Miss Rate for this system.

(b) Consider a system with multiple level memory as in Table Q52 Table Q52 (i) (ii) Component Cache Hit Rate Cache Hit Time Off Chip Cache Hit Rate Off Chip Cache Hit Time Value 90% 5 ns 96% 10 ns Main Memory Hit Rate 99.8% 60 ns Main Memory Hit Time Main Memory Miss Penalty 10 000 ns Calculate the Average Memory Access Time for this system. Calculate the Global Miss Rate for this system.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

See similar textbooks

Similar questions

If memory read cycle takes 100 ns and a cache read cycle takes 20 ns, then for four continuous references, the first one brings the main memory contents to cache and the next three from cache. Find the time taken for the Read cycle with and without Cache? What is the Percentage speedup obtained?
Consider a memory system with a cache access time of 100ns and a memory access timeof 1200ns. If the effective access time is 10% greater than the cache access time, what is thehit ratio H?
Consider a CPU with clock cycle of 10ns that executes program A in 100 clock cycles and access the memory for 50 times during the execution. The CPU uses the cache with miss rate of 7% and Miss Penalty time of 40 ns. Compare the CPU execution time with and without Cache miss
Assume the cache miss penalty is 100 clock cycles and all instructions normally take 1.0 clock cycles (ignoring memory stalls). Assume the average miss rate is 2%, there is an average of 1.5 memory references for instruction, and the average number of cache misses per 1000 instructions is 30. What is the impact on performance when behavior of the cache is included? Calculate the impact using both misses per instruc- tion and miss rate.
Assume the miss rate of an instruction cache is 4% and the miss rate of the data cache is 5%. If a processor has a CPI of 3 without any memory stalls, and the miss penalty is 50 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 44%.
A benchmark program makes 1800 memory references and produces the following statistics. The average memory access time is 60 nsec, the number of memory misses on the cache is 12,000 and the primary memory access time is 45 nsec. The computer manufacturer maintains that the Cache system has a 25 nsec access time. Is this plausible?
Let the page fault service time be 10 ms in a computer with average memory access time being 20 ns. If one page fault is generated for every 106 memory accesses, what is the effective access time for the memory.
Asap
The access time of the cache memory is 100ns and that of main memory 1000ns.It is estimated that S0percent of the memory requests are for read and the remaining 20 percent for write. The hit ratio for read accesses only is 0.9. A write through procedure is used. What is the average access time of the system considering only memory read cycles? What is the average access time of the system for both read cycles and write requests? What is the hit ratio taking into consideration the write cycles?
On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?
Design the memory mapping between the Cache memory of 512 MB to the mainmemory of 4 GB using 4 way set associative method where the block size is of 1 MB.Consider each memory location is byte addressable.
Find the AMAT for a processor with a 1 ns clock cycle time, a miss penalty of 20 clock cycles, a miss rate of 0.05 misses per instruction, and a cache access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls.