a) Suppose that in 1000 memory references there are 40 misses in L1 cache and 10 misses in L2 cache. If the miss penalty of L2 is 200 clock cycles, hit time of L1 is 1 clock cycle, and hit time of L2 is 15 clock cycles, Find the average memory access time in clock cycles.

a) Suppose that in 1000 memory references there are 40 misses in L1 cache and 10 misses in L2 cache. If the miss penalty of L2 is 200 clock cycles, hit time of L1 is 1 clock cycle, and hit time of L2 is 15 clock cycles, Find the average memory access time in clock cycles.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 22VE

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Fundamentals of Input and Output Performance

The I/O subsystem is a component of computer system design that uses buses to assist communication between the Central Processing Unit, Computer Memory/Storage, and Input and Output Devices (that is known as peripheral devices). The I/O subsystem includes disc controllers, tape drives, discs, system buses, and other devices. The I/O database application reads and writes drives using the operating system windows I/O.

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Transcribed Image Text:a) Suppose that in 1000 memory references there are 40 misses in L1 cache and 10 misses in L2 cache. If the miss penalty of L2 is 200 clock cycles, hit time of L1 is 1 clock cycle, and hit time of L2 is 15 clock cycles, Find the average memory access time in clock cycles.

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