4 Consider a microprocessor that has a block I/O transfer instruction such as that found on the 28000. Following its first execution, such an instruction takes five clock cycles to re-execute. However, if we employ a nonblocking I/O instruction, it takes a total of 20 clock cycles for fetching and execution. Calculate the increase in speed with the block I/O instruction when transferring blocks of 128 bytes.
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- 4 Consider a microprocessor that has a block I/O transfer instruction such as that found on the Z8000. Following its first execution, such an instruction takes five clock cycles to re-execute. However, if we employ a nonblocking I/O instruction, it takes a total of 20 clock cycles for fetching and execution. Calculate the increase in speed with the block I/O instruction when transferring blocks of 128 bytes. 5 A system is based on an 8-bit microprocessor and has two I/O devices. The I/O con- trollers for this system use separate control and status registers. Both devices handle data on a 1-byte-at-a-time basis. The first device has two status lines and three control lines. The second device has three status lines and four control lines. a. How many 8-bit I/O control module registers do we need for status reading and control of each device? b. What is the total number of needed control module registers given that the first device is an output-only device?Registers in RISC-V are 64-bit. For the sake of simplicity, consider the following instructions operating on 32-bit registers. Assume that registers x5 and x6 hold the values 0xBBBBBBBB and 0x00000000, respectively. What is the value in x6 for the followingslli x6, x5, 6 Using the result from the part above, what is the value in x6 for the following instruction. srli x6, x6, 6On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?
- Assignment-04. A non-pipelined CPU has 12 general purpose registers (RO, R1, R2, . Following operation are supported: R12), .... ADD Ra, Rb, Rr Add Ra to Rb and store the result in Rr MUL Ra, Rb, Rr Multiply Ra to Rb and store the result in Rr MUL operations takes two dlock cycles, ADD takes one clock cycle. Calculate minimum number of clock cycles required to compute the value of the expression XY +XYZ + YZ The variables X,Y, Z are initially available in registers RO, R1 and R2 and contents of these registers must not be modified,A 32-bit computer has 32 registers, and a memory addressed by bytes with two cycles for reading and writing operations. Consider the instruction ADD, R1, addr. This instruction adds the value stored in R1 to the value stored in the memory address addr, and stores the result in the register R1. a) Show a possible format for this instruction, having into account that the computer has 100 machine instructions and the addresses are represented using 32 bits. b) Indicate the elemental operations and control signals needed to execute the previous instruction.Consider a hypothetical computer having instruction length 32 bit and Byte addressable memory. You need to run a program P having 10 Q.4 CO4 instructions 11,12,13...10. All the instructions are stored in consecutive memory locations started from 1000. To run an instruction li, you have to complete four operations: Fetch, Decode, Execute, and Store. The content of Program Counter will be after the completion of fetch operation of instruction 12. There are no jump or branch instruction in program P
- A computer with a 32-bit 3.5 gigahertz scalar non- pipelined CPU needs to invert the colors of a 150 KB bitmap image file located in the RAM. To do this, each bit of the image must be complemented (Os are converted to 1s and vice-versa). Assume every instruction undergoes the following stages and each stage uses one CPU clock cycle: • Fetch • Decode • Read from memory • Execute • Write to memory Instructions: For this assignment, you must calculate how much time the computer will need to invert the image with a single-core and a dual core CPU. Show and explain your calculations and assumptions in a short paper and answer the following questions: • Will there be any parallel slowdown? Why or why not? Length: 2-3 page explanatory paperWe have a byte-addressable computer with fully associative mapping, 16-bit main memory addresses, and 32 cache memory blocks. The following holds true if each block is 16 bits in size:(a) Determine the number of bytes that make up the offset field.(B) Determine the exact pixel dimensions of the tag field.A microprocessor has an increment memory direct instruction, which adds 1 to the value in a memory location. The instruction has five stages: fetch opcode(four bus clock cycles),fetch operand address (three cycles), fetch operand (three cycles) add 1 to operand (three cycles), and store operand (three cycles). a. By what amount (in percent) will the duration of the instruction increase if we have to insert two bus wait states in each memory read and memory write operation? b. repeat assuming that the increment operation takes 13 cycles instead of 3 cycles
- Q.1. A computer uses a memory unit with 1024 K words of 32 bits each (as shown in the figure below). A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 registers, and an address part (15). How many bits are there in the operation code, the register code part, and the address part? Draw the instruction word format and indicate the number of bits in each part? How many bits are there in the data and address inputs of the memory?Consider a word-addressable computer with 32 bits per word. The instruction set consists of 30 different All instructions have an operation code field, a mode field to specify one of 7 possible addressing modes, a register address field to specify one of 60 available registers, and a memory address field. Each instruction is stored in one word of memory. What is the maximum allowable size for memory? Use KB, MB, or GB as a unit.Compare 0-, 1-, 2-, and 3-address machines by writing programs to computeX = (A x B + C) / (D − E × B)for each of the four machines. The instructions available for use are as follows: M is a 16-bit memory address, and X, Y, and Z are either 16-bit addresses or 4-bit registers. The0-address machine uses a stack, the 1-address machine uses an accumulator, and the other two have16 registers and instructions operating on all combinations of memory locations and registers. SUB X,Y subtracts Y from X and SUB X, Y, Z subtracts Z from Y and puts the result in X. With 8-bit opcodesand instruction lengths that are multiples of 4 bits, how many bits does each machine need to computeX?