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- An instruction pipeline has tive stages mely. instruction fetch (IF), instruction ecode and register fetch (ID/RF), instruction ocution (EX), memory access (MEM), and ester writeback (WB) with stage latencies I s 22 ns, 2 ns, I ns, and 0.75 ns, espectively (ns stands for nanoseconds). To pin in terms of frequency, the designers have decided to split the ID RF stage into threeQuestion Q: For a basic computer that is currently running in its timing TO of execution for an instruction that is located in memory location 366. The content of AC is (212) and the content of memory locations are as follow: [memory location: content]: [365:9473], [366:7010], [367:5431], [368:4620], [431:1A23], [620:C80D]. Answer the following questions that examine the contents of PC, AR, AC, DR and IR after the end of execution for the next instruction. (Note: all numbers are in Hexadecimal.) p 4:33 The content of AC after the end of * :execution for the next instruction is 700 O 620 320 O None of the choices O 4:35 /Question Q: For a basic computer that is currently running in its timing TO of execution for an instruction that is located in memory location 366. The content of AC is (212) and the content of memory locations are as follow: [memory location: content]: [365:9473], [366:7010], [367:5431], [368:4620], [431:1A23], [620:C80D]. Answer the following questions that examine the contents of PC, AR, AC, DR and IR after the end of execution for the next instruction. (.(Note: all numbers are in Hexadecimal The content of IR after the end of execution :for the next instruction is 4620 O 9473 5431 None of the choices 7010 O
- Question Q: For a basic computer that is currently running in its timing TO of execution for an instruction that is located in memory location 366. The content of AC is (212) and the content of memory locations are as follow: [memory location: content]: [365:9473], [366:7010], [367:5431], [368:4620], [431:1A23], [620:C80D]. Answer the following questions that examine the contents of PC, AR, AC, DR and IR after the end of execution for the next instruction. (Note: all numbers are in Hexadecimal.) 2 4:33 The content of AC after the end of :execution for the next instruction is 700 620 O 320 None of the choices 4:352. Suppose we have two implementations of the same instruction set architecture.Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for some programand computer B has a clock cycle time of 500 ps and a CPI of 1.2 for the sameprogram. Which computer is faster for this program and by how much?Please solve and show work. Consider two different implementations of the same instruction set architecture. The instructions can be divided into four classes according to their CPI (class A, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 2, and P2 with a clock rate of 3 GHz and CPIs of 2, 3, 2, and 2. Given a program with a dynamic instruction count of 1.0E6, instructions are divided into classes as follows: 30% class A, 20% class B, 30% class C, and 20% class D; which implementation is faster? What is the global CPI for each implementation? Find the clock cycles required in both cases.
- Consider two different implementations of the same MIPS instruction set architecture. The instructions can be divided into three classes according to their CPI (R-type, I-type, J-type). P1 with a clock rate of 2.4 GHz and CPIs of 2, 3,and 4; and P2 with a clock rate of 2.8 GHz and CPIs of 3, 3, and 3. Given a program with a dynamic instruction count of 2.0E6 instructions divided into classes as follows: 25% R-type, 35% I-type, 40% J-type, which implementation is faster? What is the global CPI for each implementation? Find the clock cycles required in both cases.Consider an instruction consisting of operation code (opcode), source register and destination identifier along with immediate operand filed. If the 32-bit processor is having 18 registers and instruction set is of size 50. What is the maximum value that an immediate operand can hold if the number system followed by processor is unsigned?In the case of a MISD machine, one example is a systolic array, which is another kind of array. It is a pipeline network, sometimes known as a "wavefront," of data processing units that is organized in the form of a network. Because execution is initiated by the receipt of new data, none of these components need the employment of a program counter throughout their operation. The computations of each unit in the clock-synchronized systolic array are performed in "lock-step," with each unit completing alternating calculation and communication phases in a single clock cycle?
- Implement the algorithm for MARIE architecture (e.g., Q3_MARIE.mas) A screenshot of the final execution states for a "test case" of your MARIE assembly code. Note your program needs to be general to take any input values using input instructions. However, a test input is used just to create a screenshot. (e.g., Q3_MARIE.PNG/JPG) The numbers of instructions in Q3_INSTRS.docx (Word document) Q3. Factorial (Iterative algorithm) - Use Q1 Get a user input of one non-negative integer numbers: A Calculate C is a factorial of A Print C Test case: A=4 Output should be 24Suppose a RISC machine uses overlapping register windows for passing parameters between procedures. The machine has 298 registers. Each register window has 32 registers, of which 10 are global variables and 10 are local variables.Q) How many registers would be available for use by output parameters?2. An implementation of the above RISC-V microprocessor has been designed where the supported instructions are classified as follows with regard to the number of cycles required to execute: Arithmetic & Logic: 4 cycles Memory Access: 5 cycles 3 cycles Branching: System Calls: 1 cycle What is the average CPI for this microprocessor? (includes lui, add, addi, or, ori, sub, and, (includes all loads and stores) (includes blt, beq, bne) (includes ecall) andi)