SYSC3320_Lab3_101089193 (1)-1

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School

Carleton University *

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Course

3320

Subject

Electrical Engineering

Date

Apr 3, 2024

Type

pdf

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2

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Rodolphe Rejouis 101089193 | CARLETON UNIVERSITY SYSC 3320-Laboratory 3 AN 8-BIT ALU DESIGN ANDIMPLEMENTATION USING VHDL AND ZYNQ-7000 SOC BOARDS FAMILY
Purpose The purpose of this lab exercise is as per the lab manual is to design and implement an ALU using VHDL code, and gain experience in synthesizing and implementing it on a Zybo board using Vivado. Deliverables: Part 1 contains deliverables for the first part of the lab and part 2 for the modified circuit. Part 1 1. Please see figure 1 and 2 for the RTL, figure 3 to 5 for the testbench. Figure 1: ALU (VHDL Code1)
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